This application relies for priority upon Korean Patent Application No. 2001-6407, filed on Feb. 9, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a complementary metal oxide silicon (CMOS) semiconductor device and method of manufacturing the same, and more particularly to a CMOS semiconductor device having polysilicon gates containing germanium (Ge) and method of manufacturing the same.
A CMOS semiconductor device is a device in which p-channel metal oxide silicon (PMOS) transistors along with n-channel metal oxide silicon (NMOS) transistors are formed to operate cooperatively with each other. In the CMOS semiconductor device, operation efficiency and speed are greatly improved as compared with a semiconductor device using only PMOS transistors and/or bipolar transistors. Accordingly, CMOS devices are commonly used as high-performance semiconductor devices. Particularly, as the elements incorporated into the device are integrated to a high degree and minimized to increase voltage characteristic and speed, a dual gate type CMOS semiconductor device, in which p-type and n-type impurities are implanted in respective polysilicon gates of corresponding impurity type transistor regions, is widely used. The dual gate type CMOS semiconductor device has the advantages of reinforcing of surface layer portions of channels and enabling symmetrical low voltage operation.
In the fabrication of the dual gate type CMOS semiconductor device, boron is usually used as a dopant doped or implanted in a polysilicon gate layer forming gate electrodes or gates of PMOS transistors. The impurity implantation of doping p-type impurity such as boron is often carried out along with an ion implantation process for forming source/drain regions.
However, where boron is used as a dopant in the impurity implantation, it may diffuse and escape into p-channels through a thin gate insulating layer, unless it is insufficiently implanted or activated. Particularly, since the gate insulating layer is formed to a very thin thickness, for example several tens of angstroms (xc3x85), the problem is more serious. If boron ions escape from the polysilicon gate layer in the impurity implantation, boron concentration in the polysilicon gate layer adjacent to the gate insulating layer will be reduced and the poly-gate depletion effect (PDE) will result.
The boron ions diffused into the gate insulating layer and the p-channels may increase p-type impurity concentration of surface layer portions of the p-channels to interconnect sources and drains, thereby resulting in a problem in which current is allowed to flow under low voltage. Also, conductivity of the gates from which the boron ions escape is decreased and thickness of the gate insulating layer is substantially increased, so that a problems of supplying insufficient voltage to the p-channels and reducing drain current may result. These contrary problems unstably vary operation voltage of the PMOS transistors, thereby deteriorating reliability of the semiconductor device. Also, the PDE may act to degrade characteristics of the gate insulating layer and the p-channels.
To solve the problems such as the PDE and degradation in characteristics of the PMOS transistors thereby, there has been proposed a method of increasing solubility of boron by adding Ge in a polysilicon gate layer forming gate electrodes or gates (IEDM, Technology Digest 1990 pp. 253-256). Since the polysilicon gate layer containing Ge has a high boron solubility, boron ions are not diffused well to the outside of the polysilicon gate layer in an annealing process and the like.
As methods of adding Ge in the polysilicon gate layer, there are a method of adding a source gas such as GeH4 gas when the polysilicon layer is formed by means of a chemical vapor deposition (CVD) method, and a method of implanting Ge ions. In the method of adding a source gas, a silicon-germanium (SiGe) gate layer is formed by injecting SiH4 gas and GeH4 gas as a source gas into a CVD chamber by means of an in situ method. In the method, the SiGe gate layer having a Ge content of 20 to 30% and a high boron solubility can be obtained. However, since the CVD is a thermal process, a photo-resist pattern cannot be used to cover partially a NMOS transistor region. Thus, the SiGe gate layer is also formed in the NMOS transistor region. Also, Ge generally shows different PDE according to the kind of dopant. Therefore, high Ge concentration or content of 20 to 30% in the SiGe layer of the NMOS transistor region may decrease solubility of n-type impurity. For example, if Ge concentration is more than 10%, at the SiGe layer of the NMOS transistor region, Ge can enlarge the PDE and can decrease capacitance to degrade characteristics of the transistors.
It has been reported that in consideration of the whole of the CMOS semiconductor device, the polysilicon gate layer should have Ge concentration of 20% (VLSI Technology Digest of Technology Papers 1998 pp. 190-191). In the case of the dual gate type CMOS semiconductor device requiring a high concentration implantation to improve performance, Ge concentration in the polysilicon gates of the NMOS and PMOS transistors should be maintained below 10% and more than 30%, respectively. However, it is difficult to satisfy these two conditions simultaneously.
Also, in the case in which Ge is contained in the polysilicon gates, for example Ge concentration is beyond 5 to 15%, there is problem that it is difficult to form titanium or cobalt silicide layer portions on the polysilicon gates. To solve the problem, a method of forming a poly-SiGe layer near a gate insulating layer and a polysilicon layer on the upper portion of the poly-SiGe layer can be used. However, in this method, it was also impossible for Ge concentration in the gates of NMOS and PMOS transistors to be maintained below 10% and more than 30%, respectively.
Accordingly, a new CMOS semiconductor device and method of manufacturing the same, which can make Ge concentration in gates of PMOS transistors to be relatively higher than that in gates of NMOS transistors, is required.
It is an object of the present invention to provide an improved CMOS semiconductor device and method of manufacturing the same, which can satisfy conditions of Ge concentration for gates of PMOS and NMOS transistors to prevent depletion of gate impurities in the gates.
It is another object of the present invention to provide an improved CMOS semiconductor device and method of manufacturing the same which can form a metal layer portion of material such as titanium and cobalt and a silicide layer portion on each polysilicon gate containing Ge.
It is another object of the present invention to provide an improved CMOS semiconductor device and method of manufacturing the same, which can increase impurity concentration of polysilicon gates to allow the device under a high integration to be operated at a low voltage.
These and other objects are provided, according to the present invention, by a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region. In accordance with the invention, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different, i.e., varies, according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate.
In the present invention, Ge concentration in a portion of polysilicon gates adjacent to the gate insulating layer is important since it is directly influenced by PDE. Accordingly, it is regarded as an effective Ge concentration of the polysilicon gates.
In one embodiment of the present invention, Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. Preferably, the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%. Alternatively, the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer can be formed of more than 30%.
In the embodiment, Ge concentration in the first polysilicon gate is abruptly reduced when the distance from the gate insulating layer is more than a given level, i.e., at a top portion thereof, to have its minimum value. In one embodiment, the minimum value of Ge concentrations is set to be below xc2xd as compared with a maximum value thereof. Also, Ge concentration in the second polysilicon gate is uniformly distributed in the range of deviation of 20% according to the distance from the gate insulating layer.
According to another aspect of the present invention, there is provided a method of manufacturing a CMOS semiconductor device. In accordance with the method, a gate insulating layer on a substrate is formed on a substrate. A SiGe layer having a Ge content of more than 20% is formed on the gate insulating layer. A silicon layer is formed on the SiGe layer. An ion implantation mask is formed on the silicon layer to cover at least one PMOS transistor region. An n-type impurity ion implantation process is performed on at least one NMOS transistor region of the substrate having the ion implantation mask. A diffusion and annealing process for controlling a distribution of Ge concentration is performed on the substrate in which n-type impurities are implanted. A gate pattern for PMOS and NMOS transistors is formed by patterning the silicon layer and the SiGe layer.
In a preferred embodiment of the invention, the method further includes forming a polysilicon seed layer before forming the SiGe layer. Preferably, the seed layer is formed of a thickness of below 100 xc3x85.
The method of the present invention further includes performing an ion implantation process to form source/drain regions in each of the NMOS and PMOS transistor regions. The method also includes performing an annealing process.
A p-type impurity ion implantation process on at least one PMOS transistor region is generally carried out along with an ion implantation process for forming source/drain regions in the PMOS transistor region. In each of the NMOS and PMOS transistor regions, source/drain regions having dual doped structures are formed by performing a light ion implantation, forming spacers on side walls of the gate pattern and performing a heavy ion implantation using the spacers and the gate pattern as a mask.
Once the ion implantation processes for forming source/drain regions are finished, subsequent heat treatment is restrained due to concern of impurity redistribution. Therefore, it is preferable that the diffusion and annealing process be carried out before performing the ion implantation process for forming source/drain regions.